Wireless communications systems are not presently capable of directly processing and generating radio frequency (RF) signals. Accordingly, wireless communication system designs will continue to employ traditional RF engineering techniques of down-converting from RF to baseband, and/or techniques of down-converting from RF to intermediate frequency (IF) signals, for processing and up-converting the processed signals for transmission.
In wireless transceivers, a wide range of frequencies may be used. In order to perform the down-conversion and/or up-conversion operations, stable and accurate frequency sources, such as crystal oscillators, are employed.
Although there exist a variety of frequency synthesis techniques, the use of phase locked loops (PLLs) remains the primary frequency synthesis methodology in wireless communications. PLLs perform frequency multiplication to generate a desired output frequency as a multiple of a reference frequency through negative feedback techniques.
Currently, most, if not all, of the PLL functionality may be implemented on a single integrated circuit (IC). Modern PLL ICs are highly integrated digital and mixed signal circuits. It is beneficial if such ICs operate on low supply voltages and consume very low power. The wide frequency range employed by modern communications transceivers may be achieved by such ICs, together with an external crystal reference, a (typically off-chip) voltage controlled oscillator (VCO) and optional external passive components.
A fractional-N PLL structure has a number of components in common with a conventional integer-N PLL structure, namely a divider circuit, a phase frequency detector (PFD), a loop filter, an amplifier and a VCO. However, a “divide by integer N” circuit, present in the conventional integer-N PLL structure, is augmented, in a fractional-N PLL structure, by a modulator, which provides the divide by integer N circuit with a divisor signal.
In a digital implementation of a fractional-N PLL structure, the modulator is implemented with an accumulator. In one implementation, known as a delta-sigma (Δ-Σ) modulator or DSM, the modulator comprises an accumulator, an integer module, a modulus module and a summer.
It should be appreciated that DSM circuitry is relatively recent technology with room for improvement.